Given a diagram, how would you verify a design/check output data. Computer arch basics and design questions
Asic Design Verification Engineer Interview Questions
273 asic design verification engineer interview questions shared by candidates
functional, code coverage ,priority encoder explanation, SV
Calculate bandwidth for 16 bit data bus, data rate: 50 MHz and only 25% of time.
1. Some simple random stimulus with specified constraints
I had a phone screen - basic SV and UVM multiple choice questions. Second round - OOPs concepts, some verification concepts (types of coverage, stimulus).
System verilog, UVM scoreboard/monitor coding
Draw a FSM sequence detector
Traversal of a binary tree to find given value
Linked list, Bit manipulation, Pipeline
Basic electronics question - 2:1 Mux, truthtable, DFF, FPGA design flow
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