How to verify a design? What do you know about your verification env? Do I know any AMBA protocol? Do I use shell script? or any other script language?
Asic Design Verification Engineer Interview Questions
273 asic design verification engineer interview questions shared by candidates
About Digital electronics and c language
how can you decide a clock cycle by 3, use verilog to impalement it
The one thing that the interviewee asked was to verify a block of test code, that was in Verilog. He just shown me a digital signal, and , then asked me to verify that waveform, according to the design. For this case, I need to write a verilog testbench.
How do you convince design team that a DUT has been thoroughly verified?
In Verilog/SystemVerilog, write a module to detect if a binary representation of a number (of length 5) is palindrome or not
All the interviewers are Indians and were really nice. I had a really good conversation each interview is about an hour. Everyone had a set of questions prepared and asking me to solve. 1. Full SV - fork join_none, virutal functions, $cast, static variable, Cache size - direct mapping, MESI FSM, constarints, parity check - post randomize 2. STA - hold violations, max freq, FIFO depth, metasibility 3. DUT - muti master muti slave bridge verification - draw the env and testcases, AXI signals 4. UVM - phases, AXI why not APB?, AXI lite vs. AXI 3.0, Driver code, coverage class and do cross coverage. 5. HR -> about team work, resources you used in a project, set back you faced. Explained most employee benefits, applying for H1B and green card, etc
How to do numerous tasks and kill off 1 task if any finish. Then wait for all to finish.
Write UVM Monitor for the defined case.
Technical
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