About UVM phases and how I use them.
Asic Design Verification Engineer Interview Questions
273 asic design verification engineer interview questions shared by candidates
Difference Between Associative array and Dynamic Arrya
Swap via value versus reference coding question. Design question about feeding data from producer to consumer (answer uses buffer)
They asked for the logic to get the maximum element in a shifted sorted array.
Clock pulse generator STA concepts
how to use UVM events and UVM pool
Basic pipelining, C/C++ and Perl coding, Verilog, FSMs, Caches
FSM pattern detector, C++ code for fibonacci sequence, swap function, linux based question to replace all instances of a word in a file with another word without opening the file, blocking/non blocking operators in verilog.
describe what is virtual function. and difference between that and pure virtual function?
Phone interview questions: 1. How do you achieve run time polymorphism? 2. What is meant by casting of objects?
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