Interviewed for a junior role, the questions were all based on work I had done previously. Nothing too technical or detailed. Questions like: Tell me about a difficult project you worked on, What do u do when you are stuck on a task?
Asic Verification Engineer Interview Questions
273 asic verification engineer interview questions shared by candidates
Virtual memory management
Full adder code, Gave some verilog codes to debug and find errors, Digital questions and Aptitude is important
How to create an interface based on an example DUT
All basics of System Verilog
mux tree, FSM, Regions, NBA, DDR, Swapping of variables, crystal oscillator, full adder using 2x1 mux
Asked about clock domain crossing, asynchronous clocks, and difference between sequential and combinational logic.
Mostly about verilog, Problem solving skills
Q: Code for algorithm to sort an array of signed integers (can't use any built in language support for sorting).
Q: Code a Verilog snippet for clock with duty cycle != 50%.
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