Basics of UVM and SV
Asic Verification Engineer Interview Questions
273 asic verification engineer interview questions shared by candidates
Tell us about yourself.
Basic system Verilog and uvm.
FSM problem. i had to write the state machime to find if the number was divisible by 3 or not. sequence detector for divisible by 3 numbers in cummulative manner.
what is a asic design?
technical- counter, data types (enum, struct), blocking and non blocking assignments. Aptitude- mixture and allegation, ratio and proportion, distance and speed, percentage, population based question.
Basic in to details and details
How would you stress test a safe lock?
Tell me about yourself.
Regarding testbench in sv and uvm
Viewing 181 - 190 interview questions
See Interview Questions for Similar Jobs
Vlsi Design EngineerFpga Design EngineerAsic Design Verification EngineerHardware Asic Design EngineerVerification EngineerRtl Design EngineerSenior Vlsi Design EngineerFpga Verification EngineerSenior Asic Verification EngineerFpga EngineerFpga DeveloperVlsi EngineerLogic Design EngineerCharacterization EngineerPhysical Design EngineerFpga Development EngineerVerificatie Design EngineerDigital Asic Design Engineer