Simplify the following circuit: One adder takes A and B as input, another adder takes C and D as input. Both adder's output connects to a MUX controlled by signal S, and the output of the MUX goes into a FF
Digital Verification Engineer Interview Questions
71 digital verification engineer interview questions shared by candidates
- Simplify truth table for a Boolean function. - Calculate setup time and hold time for a logic path. - How to fix setup and hold time violations in the path. - What is Polymorphism. - What is the difference between functional coverage and code coverage. - Given a SystemVerilog code, how is it going to execute and how variables are going to update.
What is the virtual interface and why we need it?
final state machines, microcontroler units, object oriented programming
write a Verilog code of FIFO design
Technical discussion about what I did in my career so far and what I should be doing if joining them.
Resume projects are thoroughly asked
1. What is setup and hold time? Equation and analysis wrt latch and flipflop?
What should be taken care of first? Set-up or Hold Time
How would you go about testing a counter? Explain why PCIE 6.0 has a larger header?
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