4-5 general hdl design questions, fast paced
Digital Verification Engineer Interview Questions
71 digital verification engineer interview questions shared by candidates
In round 1 - 19 MCQs related to general concepts, a mix of digital and analog electronics, mainly digital. 3 subjective question from - STA, STA, FIFO depth calculation 2 circuit design questions - FSM sequence generator , differently clock delayed output using MUX and flip flops. Round 2- Started with basic STA questions and went up to solving some on paper. Later digital design questions about mux , flip flop, counter, clock divider , FSM. Basic Verilog code like Fibonacci numbers generator , counter. MOS - MOS inverter questions and sub threshold region conduction. Short channel effects.
State Machine, Verilog code writing
They are very interested in your overall grade.
In Randomization , calculate the probability of each of the numbers but on different syntaxes.
Basic Inverters, CMOS NAND Gates, Psuedo NMOS, counter design, simple C programs and HDL programs
2. What is clock tree? Difference between clock skew and clock jitter?
How to implement a priority encoder in Verilog?
How would you describe Functional Verification
Write the VHDL or Verilog code for a given state machine diagram.
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