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Fpga Designer Interview Questions
681 fpga designer interview questions shared by candidates
How to solve setup and hold time violation, Name few techniques. Write RTL code for shift register. How to handle clock domain crossing and name few techniques. How to do floor planning. Write a RTL code latch. Design a circuit to detect 1ns asynchronous signal. What is name space in python. How to constrain asynchronous signal. When to use set max delay.
What is the most challenging project you worked on in your career?
In the screening call: quetions about your background and personal projects, then 2/3 questions on digital design basics. Questions about Verilog HDL, logic synthesis, timing constraints, metastability, finite state machines, basics of verifications, testbenches, logic gates at transistor level, application of De Morgan law, small problem on digital circuits (counters, clock dividers, FSMs).
Explain how fifo works and how metastabilty works and how to mitigate it
Implement a binary counter in VHDL?
Based on FPGA Application Engineer role.
Can't remember.
Delay the bus signal with BRAM.
Easy questions like write DFF etc.
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