A rudimentary sort of #s in PERL, no design verification questions.
Senior Verification Engineer Interview Questions
189 senior verification engineer interview questions shared by candidates
mostly UVM verification methodologies and insight on how to debug.
explain me why uvm methodology ?
SV UVM based question, purpose of uvm_config_db, uvm testbench architecture
In SV and UVM started with basics and went deep while process is going on
Design a circuit for edge detection circuit
Define performance?
About work experience, Implement randc using rand, SV questions, Verilog design question, Fifo depth question, Scoreboard implementation of a design, MESI, Linked list traversing question. Looks like they need C++ even if the position requires SV/UVM only.
Shown a perl code, what does it do?
random, depends on team
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