Senior Verification Engineer Interview Questions

189 senior verification engineer interview questions shared by candidates

1. Protocol Questions which Individual worked on. 2. UVM Phases and what are Bottom up and what are top down ? 3. How System/Processor boots and what are the steps to compile and execute the 'C' Code 4. How to call task inside a function ? 5. Difference between automatic and static variables ? 6. what is the makefile and what are the contents of makefile ? How to run the makefile ?
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Senior Verification Engineer

Interviewed at PerfectVIPs

3.5
May 4, 2016

1. Protocol Questions which Individual worked on. 2. UVM Phases and what are Bottom up and what are top down ? 3. How System/Processor boots and what are the steps to compile and execute the 'C' Code 4. How to call task inside a function ? 5. Difference between automatic and static variables ? 6. what is the makefile and what are the contents of makefile ? How to run the makefile ?

In Person: -simple assembly instructions, verify hazards -complex design, methodology for verification -design memory in c, run times -rotate sorted array, binary search algo with shifted array -reverse linked list
avatar

Senior Verification Engineer

Interviewed at NVIDIA

4.4
Nov 1, 2016

In Person: -simple assembly instructions, verify hazards -complex design, methodology for verification -design memory in c, run times -rotate sorted array, binary search algo with shifted array -reverse linked list

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