A packet with address, and data. The address range is split into 4 regions. Create a class that will generate 100 packets and cover all possible ranges.
Senior Verification Engineer Interview Questions
189 senior verification engineer interview questions shared by candidates
Code some black box RTL in verilog
1. finding the probability of possible combiations of a radom variable with given constraints. 2. Question related to System Verilog Assertions.
Verification concepts.
See above. All questions are from daily work.
write Sv constraints uvm phases
FIFO verification (seems to be everyone's favourite) and another one that I won't give away and an easy coding exercise (pretty much fizzbuzz level).
Hr questioning with character related question which is not difficult but you can never been will prepared for
real case study and asking for solution with the problem in real life
Related to SV + UVM + Puzzles + Perl and other scripting language
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