Tell us a time that you faced a technical challenge and how you overcame it.
Verification Design Engineer Interview Questions
3,721 verification design engineer interview questions shared by candidates
Questions were from computer architecture, cache verification, cpu and memory systems
Describe Yourself, project related question.
How do I feel today
Basic sv and uvm and some digital verilog.
1. Difference between inter assignment and intra assignment delay 2. Blocking and Non- blocking procedural block 3. How to design AND gate using MUX 4. Signals used in FIFO. 5. Do FIFO required address or not? 6. What do you understand by synchronous and asynchronous circuit. 7. How can we disable the randomisation ? 8. Why we use virtual interface in verification environment? 9. How to select and give in the particular testcase which were generated in generator block?
Started with self introduction What's your role in project What is constraints Clocking block Modport FIFO Polymorphism
Which area are you specialized in?
Fota overview diagnostic flashing test and defect management procedure
What is that interest you about N26?
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