define tlm fifo's?
Verification Design Engineer Interview Questions
3,721 verification design engineer interview questions shared by candidates
Digital and SV ,UVM verilog basis
What is the difference between task and function
They asked whether I am comfortable to do this verification work, and we just have to verify the data of the onboarding members in sale or customer department. Questions based on small data including basic excel.
- code coverage: types, why, how to collect, analysis. Functional coverage: why, how, analysis.
- structure of a typical verification environment, explain each block. Verification closure process. Top/chip level verification, block level reuse techniques.
- problem solving: 1) write systemverilog properties to verify a given, simple protocol. 2) compute the optimal FIFO depth given the in and out timing specs. 3) Write the RTL for a FSM then synthesize it.
Mostly about verilog, Problem solving skills
Verilog based basic questions , SV and UVM questions
What can you do for this company?
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