How to wright constraint for division of two without using modulus?
Verification Design Engineer Interview Questions
3,721 verification design engineer interview questions shared by candidates
How comfortable are you learning new tools ?
Why do you want to work for Lowers risk group?
Q: Code for algorithm to sort an array of signed integers (can't use any built in language support for sorting).
Q: Code a Verilog snippet for clock with duty cycle != 50%.
Strengths? What will you bring to the company? Past experiences?
I was basically asked about information given in my resume, such as university projects and my programming skills. I had to describe some projects in which I had to find and correct errors. I was asked where I would see me in five years and what I was looking for now.
What did you do in your last position?
Can you try selling a pen to me through the phone?
1. Question on FSM 2. Counter verilog code 3. Aptitude question: How many attempts are needed to identify the max floor at which the egg doesn't break
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