Verification Design Engineer Interview Questions

3,719 verification design engineer interview questions shared by candidates

Node insertion in linked list. Fibonacci series function, hardware to generate Fibonacci series, prime number generation hardware , STA concepts, clock domain crossing, use of synchronizes, skew and setup hold time violation.
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ASIC Verification Engineer

Interviewed at Qualcomm

3.8
Jul 17, 2011

Node insertion in linked list. Fibonacci series function, hardware to generate Fibonacci series, prime number generation hardware , STA concepts, clock domain crossing, use of synchronizes, skew and setup hold time violation.

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