All questions were related to my previous experience, testing methodology, and problem solving skills. They also asked some basic oo concepts
Verification Design Engineer Interview Questions
3,719 verification design engineer interview questions shared by candidates
Difference between verilog and sv.? Basic interface questions.
What is one hot encoding?
Why Qualcomm?
question around the system verilog ,verification methodology.
FSM for sequence detector. Verification environment. Verilog programming.
How to set config_cb from lower to higher hierarchy
OOPs questions and also ASIC and Verfication based questions
what do u know about virtual pages
pass by value, pass by ref, function in c for fibonacci, pattern detector fsm, pipeline hazard
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