Questions related to Pipelining, Interrupt Handling.
Asic Verification Engineer Interview Questions
273 asic verification engineer interview questions shared by candidates
Write constraints for unique elements in an array. Write assertions for different scenarios of AXI protocol. Basics of UVM including testbench components, phases, TLM ports.
Questions on protocols like API, AXI, AHB, API, UART.
1)Driver sequencer handshake.
* job experience and roles * how do u verify a scheduler * A block has inputs of network pkts and buffers/pipelines them through an RTL. RTL has counters which will tell how many packets are sent. How to verify? (Counters Read => count. Write => clear) How to verify counts? what cases will u test? * Given a sys verilog code for a memory model and asked to implement read/write/move functions and write checks
Systemverilog and UVM questions
They asked me 1)about the various concepts of verifying a design and also provided me scenarios as to how we can verify them . 2)to explain my previous projects and my responsibilities for each of the projects . 3)Also, the software team asked me a programming example. There were various teams of people wanting me to explain my previous job profile and responsibilities and explaining me about their company culture. Overall, It was a very good experience for me since I was fascinated by the fact that my job profile and trading can coincide !! and how!
Question regarding Logic design, Verilog ,State Machine- pattern detection, Comp Arch- Pipeline, hazards, cache, associativity, Basic Perl were asked.
Basic computer architecture questions, pipeline concepts and hazards. FSM for a sequence detector. Fibonacci using recursion and linked list reversal. Some scripting question which i could not answer.
Scripting questions on 2D hashes and asked for coding in perl/python. Basic questions on STA
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