UVM, system verilog, C++, puzzles and ethernet related
Asic Verification Engineer Interview Questions
273 asic verification engineer interview questions shared by candidates
Using constrained randomization what types of functional coverage would you expect to see on a PCIe bus?
Why I want to join
As an ASIC verification Engineer Most of the questions were based on system Verilog and UVM. 1: Components of UVM, which components have you worked. 2: Phases in UVM 3: Assertions
They mostly concentrated on sv , uvm
Regarding Technical skills I don't have any difficulties and regarding job location to change from Bangalore can be difficult
not much difficult
Which project should I question you about?
Basic questions on Verilog Combinational and sequential coding differences, Coding a state machine, Timing problems Was asked to explain my projects
rate yourself in c and vlsi
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