What's your name , is it [name] ?
Asic Verification Engineer Interview Questions
273 asic verification engineer interview questions shared by candidates
Current project architecture and role. SV and UVM related. SV constraint, coverage, assertions. UVM architecture and flow. Verification strategy related.
where do you see yourself in 5 years
They asked me 1)about the various concepts of verifying a design and also provided me scenarios as to how we can verify them . 2)to explain my previous projects and my responsibilities for each of the projects . 3)Also, the software team asked me a programming example. There were various teams of people wanting me to explain my previous job profile and responsibilities and explaining me about their company culture. Overall, It was a very good experience for me since I was fascinated by the fact that my job profile and trading can coincide !! and how!
Tell me about a class you like?
Write TB for one of the projects from past experience . Describe its features and implement DUT interface connections and build TB on whiteboard .
Basics on ddr verification and functional coverage
Q: Basics of system verilog classes, creating parent class object using child class handle, $cast concept. Fork-join processes, how is control handed to code outside the fork in the 3 cases; code a watch-dog timer to time out if an event does not occur by the end of certain transaction.
Digital electronics, Perl, Verification flow
What is difference between dynamic and associative array.
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