Given a diagram, how would you verify a design/check output data. Computer arch basics and design questions
Asic Verification Engineer Interview Questions
273 asic verification engineer interview questions shared by candidates
functional, code coverage ,priority encoder explanation, SV
Calculate bandwidth for 16 bit data bus, data rate: 50 MHz and only 25% of time.
1. Some simple random stimulus with specified constraints
I had a phone screen - basic SV and UVM multiple choice questions. Second round - OOPs concepts, some verification concepts (types of coverage, stimulus).
System verilog, UVM scoreboard/monitor coding
Draw a FSM sequence detector
Traversal of a binary tree to find given value
Linked list, Bit manipulation, Pipeline
Basic electronics question - 2:1 Mux, truthtable, DFF, FPGA design flow
Viewing 251 - 260 interview questions
See Interview Questions for Similar Jobs
Vlsi Design EngineerFpga Design EngineerAsic Design Verification EngineerHardware Asic Design EngineerVerification EngineerRtl Design EngineerSenior Vlsi Design EngineerFpga Verification EngineerSenior Asic Verification EngineerFpga EngineerFpga DeveloperVlsi EngineerLogic Design EngineerCharacterization EngineerPhysical Design EngineerFpga Development EngineerVerificatie Design EngineerDigital Asic Design Engineer