Design a circuit which outputs a pulse when the input flips. The input is synchronous to a clock.
Asic Verification Engineer Interview Questions
273 asic verification engineer interview questions shared by candidates
How to solve a specific problem.
Data Structures: Linked Lists , Binary Search Tree Concept and Complexity. Hash Tables in C++/Python. C++: Private vs Public Pass by Value vs Pass by Reference Pointer vs Reference Computer Architecture: Pipelining What is Cache & Cache Performance (Hardware & Software) Cache Architecture Virtual Adress Address Translation TLB Explain your Class/Internship Project
What is a NAND gate
they focused a lot on OOP, which is unexpected given the title that I applied.
Launch 5 (t1,t2,t3,t4,t5) tasks in parallel, wait for 4 of the tasks to be done and kill the task t3.
FIFO Design was the toughest of all the questions they asked me
fork-join use in a sequence. UVM Test bench architecture. Virtual interface requirement. etc.
No difficult questions
Coding in C to output Fibonacci
Viewing 41 - 50 interview questions
See Interview Questions for Similar Jobs
Vlsi Design EngineerFpga Design EngineerAsic Design Verification EngineerHardware Asic Design EngineerVerification EngineerRtl Design EngineerSenior Vlsi Design EngineerFpga Verification EngineerSenior Asic Verification EngineerFpga EngineerFpga DeveloperVlsi EngineerLogic Design EngineerCharacterization EngineerPhysical Design EngineerFpga Development EngineerVerificatie Design EngineerDigital Asic Design Engineer